1. Field of the Invention
The present invention relates to a Dynamic Random Access Memory incorporating a self refresh control circuit for performing a self refresh operation for a plurality of memory cells in a memory cell array in the DRAM, and, more particularly, to a DRAM having a self refresh control circuit capable of easily changing the period of the self refresh operation with a desired period and thereby reducing a power consumption of the DRAM during a stand-by state.
2. Description of the Prior Art
In conventional DRAM devices, one has been disclosed in U.S. Pat. No. 5,321,662, for example, a period (or a cycle) of a self refresh operation (or a self refreshing) is fixed, not changed by a programmable method, and it is also difficult to detect the period of the self refresh by external devices. Accordingly, in the conventional DRAM devices, it is difficult to perform the self refresh at an optimum period. This causes an increase in the power consumption of the DRAM devices. In particular, there is a drawback that the power consumption of a DRAM device not having an optimum period or cycle of the self refresh operation is larger when compared with a DRAM device having the optimum period of the self refresh operation.
In addition, in the conventional DRAM devices described above, because it is difficult to change the period of the self refresh operation according to demand, there is a drawback that it is difficult to perform the operation test for the DRAM devices by using various periods in the self refresh operation.
As described above, since the conventional DRAM devices have fixed periods of the self refresh, that is, it is thereby difficult to change the period of the self refresh operation for the DRAM devices by a programmable method according to need, and it is also difficult to currently detect the period of the self refresh, so that it is difficult to set the optimum period of the self refresh operation for each DRAM device, and so that it is thereby difficult to make a DRAM of a low power consumption. Furthermore, in the past, it is also difficult to perform the operation test for each DRAM device by changing the period of the self refresh operation to a desired period.